Practical Engineering
open-menu closeme
Engineering
github linkedin rss
  • False data independency: a look at cache line and write combining

    calendar Feb 23, 2024 · 7 min read · Go Computer Architecture  ·
    Share on: twitter copy

    Modern CPUs operate significantly faster than memories. A 4.5 GHz x64 CPU operates 30 times faster than a 6000 MHz DDR5 memory of CAS Latency 36. Adding latencies incurred by the bus and memory coherency protocols, memory could be 100 times slower than registers. To mitigate the speed gap, CPU uses layers of caches, …


    Read More

Peng Zhang

Software Engineer

Recent Posts

  • A few Go idioms
  • A Few Shell Surprises
  • x509: certificate signed by unknown authority? Maybe the cert pool is empty
  • Lessons from an errgroup and Context mishap
  • Avoid panic on expected errors: lessons from operating journald-to-cwl
  • GPG is still in use to verify downloads
  • Why does GOMEMLIMIT take up significant physical memory for unused virtual memory?
  • Logs default to stderr in Go and other languages: avoid using stderr to determine program success.

Tags

GO 16 ALGORITHMS 8 INTERVIEW 7 LINUX 7 GUIDE 3 CONTAINER 2 DISTRIBUTED-SYSTEM 2 WEB 2 BOTTLEROCKET 1 COMPUTER-ARCHITECTURE 1 CONCURRENCY 1 CRYPTOGRAPHY 1 DATABASES 1 SELINUX 1
All Tags
ALGORITHMS8 BOTTLEROCKET1 COMPUTER-ARCHITECTURE1 CONCURRENCY1 CONTAINER2 CRYPTOGRAPHY1 DATABASES1 DISTRIBUTED-SYSTEM2 GO16 GUIDE3 INTERVIEW7 LINUX7 SELINUX1 SHELL1 TESTING1 WEB2
[A~Z][0~9]
Peng Zhang

Copyright 2022-  PENG ZHANG. All Rights Reserved

to-top